Aislyn Technologies Pvt Ltd



Passion for Learning

VLSI

Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining thousands of transistors into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is a VLSI device. Before the introduction of VLSI technology most ICs had a limited set of functions they could perform. An electronic circuit might consist of a CPU, ROM, RAM and other glue logic. VLSI lets IC designers add all of these into one chip.

Applications of VLSI Design:
• Application-specific integrated circuit
• Caltech Cosmic Cube
• Design rules checking
• Electronic design automation
• Poly silicon
• Mead & Conway revolution

Titles

  1. HIGH-SPEED AND ENERGY-EFFICIENT CARRY SKIP ADDER OPERATING UNDER A WIDE RANGE OF SUPPLY VOLTAGE LEVELS
  2. DESIGN AND ANALYSIS OF INEXACT FLOATING-POINT ADDERS
  3. HIGH-SPEED, LOW-POWER, AND HIGHLY RELIABLE FREQUENCY MULTIPLIER FOR DLL-BASED CLOCK GENERATOR
  4. HIGH-SPEED HYBRID-DOUBLE MULTIPLICATION ARCHITECTURES USING NEW SERIAL-OUT BIT-LEVEL MASTROVITO MULTIPLIERS
  5. LOW-DELAY AES POLYNOMIAL BASIS MULTIPLIER
  6. A MODIFIED PARTIAL PRODUCT GENERATOR FOR REDUNDANT BINARY MULTIPLIERS
  7. SCALABLE GF(P) MONTGOMERY MULTIPLIER BASED ON A DIGIT–DIGIT COMPUTATION APPROACH
  8. HIGH-SPEED POLYNOMIAL BASIS MULTIPLIERS OVER GF (2 M) FOR SPECIAL PENTANOMIALS
  9. PRE-ENCODED MULTIPLIERS BASED ON NON-REDUNDANT RADIX-4 SIGNED-DIGIT ENCODING
  10. JOINT DATA FILTERING AND LABELING USING GAUSSIAN PROCESSES AND ALTERNATING DIRECTION METHOD OF MULTIPLIERS
  11. LOW-COST HIGH-PERFORMANCE VLSI ARCHITECTURE FOR MONTGOMERY MODULAR MULTIPLICATION
  12. HIGH-PERFORMANCE PIPELINED ARCHITECTURE OF ELLIPTIC CURVE SCALAR MULTIPLICATION OVER GF(2M)
  13. A NEW PARALLEL VLSI ARCHITECTURE FOR REAL-TIME ELECTRICAL CAPACITANCE TOMOGRAPHY
  14. MACS: A HIGHLY CUSTOMIZABLE LOW-LATENCY COMMUNICATION ARCHITECTURE
  15. A CELLULAR NETWORK ARCHITECTURE WITH POLYNOMIAL WEIGHT FUNCTIONS
  16. EKHO: A 30.3W, 10K-CHANNEL FULLY DIGITAL INTEGRATED 3-D BEAMFORMER FOR MEDICAL ULTRASOUND IMAGING ACHIEVING 298M FOCAL POINTS PER SECOND
  17. A 128-CHANNEL EXTREME LEARNING MACHINE-BASED NEURAL DECODER FOR BRAIN MACHINE INTERFACES
  18. LOW-POWER/COST RNS COMPARISON VIA PARTITIONING THE DYNAMIC RANGE
  19. A LOW-POWER BROAD-BANDWIDTH NOISE CANCELLATION VLSI CIRCUIT DESIGN FOR IN-EAR HEADPHONES
  20. FLEXIBLE DSP ACCELERATOR ARCHITECTURE EXPLOITING CARRY-SAVE ARITHMETIC
  21. UNEQUAL-ERROR-PROTECTION ERROR CORRECTION CODES FOR THE EMBEDDED MEMORIES IN DIGITAL SIGNAL PROCESSORS
  22. A 5-GB/S 2.67-MW/GB/S DIGITAL CLOCK AND DATA RECOVERY WITH HYBRID DITHERING USING A TIME-DITHERED DELTA–SIGMA MODULATOR
  23. AN ALL-DIGITAL APPROACH TO SUPPLY NOISE CANCELLATION IN DIGITAL PHASE-LOCKED LOOP
  24. TRIGGER-CENTRIC LOOP MAPPING ON CGRAS
  25. ON EFFICIENT RETIMING OF FIXED-POINT CIRCUITS
  26. DESIGN AND IMPLEMENTATION OF HIGH-SPEED ALL-PASS TRANSFORMATION-BASED VARIABLE DIGITAL FILTERS BY BREAKING THE DEPENDENCE OF OPERATING FREQUENCY ON FILTER ORDER
  27. PRE-ENCODED MULTIPLIERS BASED ON NON-REDUNDANT RADIX-4 SIGNED-DIGIT ENCODING
  28. LOW-POWER ECG-BASED PROCESSOR FOR PREDICTING VENTRICULAR ARRHYTHMIA
  29. PROCESS VARIATION DELAY AND CONGESTION AWARE ROUTING ALGORITHM FOR ASYNCHRONOUS NOC DESIGN
  30. HIGH-PERFORMANCE DEADLOCK-FREE ID ASSIGNMENT FOR ADVANCED INTERCONNECT PROTOCOLS
  31. A RELAXED MIN-SUM LDPC DECODER WITH SIMPLIFIED CHECK NODES
  32. A NEW BINARY-HALVED CLUSTERING METHOD AND ERT PROCESSOR FOR ASSR SYSTEM
  33. ALGORITHM AND ARCHITECTURE OF CONFIGURABLE JOINT DETECTION AND DECODING FOR MIMO WIRELESS COMMUNICATIONS WITH CONVOLUTIONAL CODES
  34. INPUT-BASED DYNAMIC RECONFIGURATION OF APPROXIMATE ARITHMETIC UNITS FOR VIDEO ENCODING
  35. A HIGH-PERFORMANCE FIR FILTER ARCHITECTURE FOR FIXED AND RECONFIGURABLE APPLICATIONS
  36. A LOW-COST, RADIATION-HARDENED METHOD FOR PIPELINE PROTECTION IN MICROPROCESSORS
  37. A FAST FAULT-TOLERANT ARCHITECTURE FOR SAUVOLA LOCAL IMAGE THRESHOLDING ALGORITHM USING STOCHASTIC COMPUTING
  38. FAULT TOLERANT PARALLEL FFTS USING ERROR CORRECTION CODES AND PARSEVAL CHECKS
  39. SPECULATIVE LOOKAHEAD FOR ENERGY-EFFICIENT MICROPROCESSORS
  40. SOURCE CODE ERROR DETECTION IN HIGH-LEVEL SYNTHESIS FUNCTIONAL VERIFICATION
  41. VLSI DESIGN FOR CONVOLUTIVE BLIND SOURCE SEPARATION
  42. ARGO: A REAL-TIME NETWORK-ON-CHIP ARCHITECTURE WITH AN EFFICIENT GALS IMPLEMENTATION
  43. DESIGN OF A NETWORK OF DIGITAL SENSOR MACROS FOR EXTRACTING POWER SUPPLY NOISE PROFILE IN SOCS
  44. DISTRIBUTED SENSOR NETWORK-ON-CHIP FOR PERFORMANCE OPTIMIZATION OF SOFT-ERROR-TOLERANT MULTIPROCESSOR SYSTEM-ON-CHIP
  45. ASSESSING THE SUITABILITY OF KING TOPOLOGIES FOR INTERCONNECTION NETWORKS
  46. FCUDA-NOC: A SCALABLE AND EFFICIENT NETWORK-ON-CHIP IMPLEMENTATION FOR THE CUDA-TO-FPGA FLOW
  47. A NEW CDMA ENCODING/DECODING METHOD FOR ON-CHIP COMMUNICATION NETWORK
  48. HIGH-PERFORMANCE NB-LDPC DECODER WITH REDUCTION OF MESSAGE EXCHANGE
  49. STREAMING ELEMENTS FOR FPGA SIGNAL AND IMAGE PROCESSING ACCELERATORS
  50. CONCEPT, DESIGN, AND IMPLEMENTATION OF RECONFIGURABLE CORDIC
  51. SYMBIOTE COPROCESSOR UNIT—A STREAMING COPROCESSOR FOR DATA STREAM ACCELERATION
  52. VANUCA: ENABLING NEAR-THRESHOLD VOLTAGE OPERATION IN LARGE-CAPACITY CACHE
  53. CODE COMPRESSION FOR EMBEDDED SYSTEMS USING SEPARATED DICTIONARIES
  54. EFFICIENCY ENABLERS OF LIGHTWEIGHT SDR FOR MIMO BASEBAND PROCESSING
  55. DESIGN AND ANALYSIS OF A LOW-POWER READOUT CIRCUIT FOR CDZNTE DETECTORS IN 0.13- M CMOS
  56. POWER EFFICIENT LEVEL SHIFTER FOR 16 NM FINFET NEAR THRESHOLD CIRCUITS
  57. LBA SCRAMBLER: A NAND FLASH AWARE DATA MANAGEMENT SCHEME FOR HIGH-PERFORMANCE SOLID-STATE DRIVES
  58. A SINGLE-STAGE LOW-DROPOUT REGULATOR WITH A WIDE DYNAMIC RANGE FOR GENERIC APPLICATIONS
  59. A 6 B 5 GS/S 4 INTERLEAVED 3 B/CYCLE SAR ADC
  60. A 3-D CPU-FPGA-DRAM HYBRID ARCHITECTURE FOR LOW-POWER COMPUTATION
  61. PSI CONSCIOUS WRITE SCHEDULING: ARCHITECTURAL SUPPORT FOR RELIABLE POWER DELIVERY IN 3-D DIE-STACKED PCM
  62. CLAP: CLUSTERED LOOK-AHEAD PREFETCHING FOR ENERGY-EFFICIENT DRAM SYSTEM
  63. FLEXIBLE ECC MANAGEMENT FOR LOW-COST TRANSIENT ERROR PROTECTION OF LAST-LEVEL CACHES
  64. A LOW-POWER BROAD-BANDWIDTH NOISE CANCELLATION VLSI CIRCUIT DESIGN FOR IN-EAR HEADPHONES
  65. MULTIPLE-VALUED SIGNALING FOR HIGH-SPEED SERIAL LINKS USING TOMLINSON-HARASHIMA PRECODING
  66. VLSI IMPLEMENTATION OF FULLY-PARALLEL LTE TURBO DECODERS
  67. A NEW BINARY-HALVED CLUSTERING METHOD AND ERT PROCESSOR FOR ASSR SYSTEM
  68. A 128-CHANNEL EXTREME LEARNING MACHINE-BASED NEURAL DECODER FOR BRAIN MACHINE INTERFACES
  69. A LOW-COST, RADIATION-HARDENED METHOD FOR PIPELINE PROTECTION IN MICROPROCESSORS
  70. LOW-POWER/COST RNS COMPARISON VIA PARTITIONING THE DYNAMIC RANGE
  71. EXPLORATION OF LOW-POWER HIGH-SFDR CURRENT-STEERING D/A CONVERTER DESIGN USING STEEP-SLOPE HETEROJUNCTION TUNNEL FETS
  72. A 2 ΜW 45 NV/√HZ READOUT FRONTEND WITH MULTIPLE CHOPPING, ACTIVE-HIGH-PASS RIPPLE REDUCTION LOOP AND PSEUDO-FEEDBACK DC SERVO LOOP
  73. A SINGLE-ENDED WITH DYNAMIC FEEDBACK CONTROL 8T SUBTHRESHOLD SRAM CELL
  74. AN IMPROVED DCM-BASED TUNABLE TRUE RANDOM NUMBER GENERATOR FOR XILINX FPGA
  75. Measuring Improvement When Using HUB Formats To Implement Floating-Point Systems Under Round-To-Nearest
  76. A HIGH-THROUGHPUT VLSI ARCHITECTURE FOR HARD AND SOFT SC-FDMA MIMO DETECTORS
  77. DESIGN AND ANALYSIS OF APPROXIMATE COMPRESSORS FOR MULTIPLICATION
  78. INPUT VECTOR MONITORING SCHEME USING A STATIC-RAM LIKE STRUCTURE
  79. FPGA IMPLEMENTATION OF A LOW COMPLEXITY STEGANOGRAPHIC SYSTEM FOR DIGITAL IMAGES
  80. A DISCRETE TCHEBICHEF TRANSFORM APPROXIMATION FOR IMAGE AND VIDEO CODING
  81. A LOW-COST HARDWARE ARCHITECTURE FOR ILLUMINATION ADJUSTMENT IN REAL TIME APPLICATION
  82. LOW-ENERGY TWO-STAGE ALGORITHM FOR HIGH EFFICACY EPILEPTIC SEIZURE DETECTION
  83. FAULT TOLERANT PARALLEL FILTERS BASED ON ERROR CORRECTION CODES
  84. A RECONFIGURABLE SMART SENSOR INTERFACE FOR INDUSTRIAL
  85. A TOPOLOGY-BASED MODEL FOR RAILWAY TRAIN CONTROL SYSTEMS
  86. AUTOMATED MOBILITY AND ORIENTATION SYSTEM FOR BLIND OR PARTIALLY
  87. LOW-COST CONTROL FLOW PROTECTION VIA AVAILABLE REDUNDANCIES IN THE MICROPROCESSOR PIPELINE
  88. LOW-POWER PROGRAMMABLE PRPG WITH TEST COMPRESSION CAPABILITIES
  89. A LOW-POWER ARCHITECTURE FOR THE DESIGN OF A ONE-DIMENSIONAL MEDIAN FILTER
  90. SOURCE CODING AND PRE EMPHASIS FOR DOUBLE-EDGED PULSE WIDTH MODULATION SERIAL COMMUNICATION
  91. HIGH PERFORMANCE DEADLOCK FREE ID ASSIGNMENT FOR ADVANCED INTERCONNECT PROTOCOLS
  92. A HIGH PERFORMANCE ON CHIP BUS (MSBUS) DESIGN AND VERIFICATION
  93. IN-FIELD TEST FOR PERMANENT FAULTS IN FIFO BUFFERS OF NOC ROUTERS
  94. EFFICIENT DYNAMIC VIRTUAL CHANNEL ORGANIZATION AND ARCHITECTURE FOR NOC SYSTEMS